The Journal of SMT is a peer-reviewed, open access, technical publication of articles related to electronics manufacturing technologies, including microsystems, emerging technologies, and related business operations.
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Liquid Metal Paste Jetting for High-Performance Computing Applications in Electronics Assembly
Metals have long been used as thermal interface materials (TIMs). Due to their high reliability and thermal conductivity, metal TIMs are excellent solutions for heat dissipation in electronic systems, especially for more challenging applications. Thermal conductivity and interfacial resistance are the most important properties of TIM. One of the biggest obstacles for using metal TIMs is interfacial resistance. Most metal TIMs are quite stiff and require compressive force to maintain necessary contact with active components to lower the interfacial resistance. With devices becoming smaller, consuming more power, and producing more heat, finding the right TIM becomes a highly critical step in any electronic systems application. Recently, liquid metal TIMs have gained popularity, especially for thermal management of high-performance computing semiconductor applications such as in central processing units (CPUs), graphics processing units (GPUs), and multi-chip modules (MCMs). Due to their fluid nature, liquid metal TIMs do not need to be compressed to maintain even contact, and they can accommodate imperfections in the neighboring components. The newest metal TIMs are made of liquid metal paste (LMP). These gallium-based, high viscosity materials maintain all the good properties of liquid metals but also offer some improved mechanical properties. A key challenge lies in applying LMPs consistently through various dispensing techniques which could be traditional, like time-pressure versus advanced jetting technology. Both dispensing techniques will be compared based on dispensing quality, weight repeatability on substrates, and valve-hardware stability. This paper addresses the challenges faced during LMP dispensing in high-volume manufacturing, and how to maintain constant volume over the product with good dispense quality leading to higher throughput and process reliability.
Dispensing, high-performance computing (HPC), jetting, liquid metal (LM), liquid metal paste (LMP), phase change metal (PCM), printed circuit board (PCB), thermal interface material (TIM)
Copyright (c) 2026 SUNNY AGARWAL, Milos Lazic https://creativecommons.org/licenses/by-nc-nd/4.0
Exploring the Next-generation High-Reliability Lead-free Solder Alloy
The ever-increasing demand for high-temperature reliability and extended fatigue life requirements in more demanding electronic applications, has motivated further investigation on high-reliability lead-free solder alloys. The novel Alloy 10 solder alloy presented here exhibits exemplary thermomechanical and mechanical reliability in extreme operating conditions, ideal for the future needs of high-reliability electronics, such as in the automotive industry. Recent results showing excellent performance of Alloy 10 when compared to another leading high-reliability alloy, have also raised questions on which features are responsible for such performance. In this work, we present the latest results of a collaborative in-depth study to understand the mechanisms behind the Alloy 10 solder alloy’s improved performance. Solder joint samples are studied for the detailed composition and distribution of phases after reflow and aging treatment under varying aging times. The effect of aging time and temperature on the evolution of the microstructure of the solder joints is then studied. A redistribution of elements and phases are observed after aging; microconstituents are observed to be uniformly distributed after prolonged aging, while intermetallic compounds grow and become distinctly visible upon aging. This discussion is then further expanded by discussing the mechanical behaviour of Alloy 10 as measured by a custom designed micro-precision mechanical tester, which was used to perform isothermal creep, monotonic and fatigue testing of solder test specimens under shear at room temperature. Thermal cycling has also been performed on BGA solder joints in extreme temperature conditions and results have been discussed.
High-reliability, automotive, aging, microstructure
Copyright (c) 2026 Pritha Choudhury, Prathap Augustine, Paul Salerno, Anna Lifton, John Blendell, Ganesh Subbarayan, Lijia Xie, Sean Yenyu Lai https://creativecommons.org/licenses/by-nc-nd/4.0
Development of Si-Interposers for 3D Heterogeneous Integration
BRIDG (Bridging the Innovation Development Gap) is working with our foundry operator Skywater to establish a domestic supply chain for Si-Interposers with and without through silicon vias (TSVs). BRIDG is leveraging a strategic advanced packaging partnership with imec by licensing and transferring the imec silicon interposer technology to the Center for NeoVation in NeoCity, Florida, making the State-of-the-Art technology available to the US Industrial Base for low volume production. Si-Interposers provide a platform to assemble multiple types of chips (chiplets) to achieve a very high-density multi-chip module. This is especially important when accommodating very fine pitched die (50um and less) that require a higher density circuity (1um lines/spaces L/S and less) offered by a semiconductor back end of line (BEOL) process. Current metallization processes used for organic substrates can only effectively go down to about 5um, which limit the die pitch to 150um or greater. Future chiplet designs are projected to scale below 20um pitch, and this is where Si-Interposers offer the advantage. Two silicon interposer electrical qualification vehicles will be discussed in this paper. The first one is a bridge interposer, having two metal Cu Damascene layers with 1um lines/space on a Si-substrate with a body size of 9mm x 13mm. The second electrical qualification vehicle has the same body structure along with through silicon vias (TSVs) having dimensions of 10um x 100um. For these two offerings, the basic process flows will be presented, along with supporting technical data. In addition, examples of applications for both offerings will be presented.
Copyright (c) 2025 Journal of Surface Mount Technology
A New Efficient Thermomechanical Reliability Model for Lead-Free Solder Joints
The thermomechanical reliability of solder joints remains a challenge for companies whose electronic equipment is used in harsh thermal conditions throughout their lifecycle, such as in the aeronautics, space, military or medical applications. With the RoHS legislation and REACh directive preventing lead from being used in electronic equipment, 96.5Sn-3.0Ag-0.5Cu (SAC305) composition has become one of the most widely used lead-free solder alloys. Various models are available to evaluate the reliability of solder joints under temperature cycles, ranging from simple analytical models to complex Finite Element Analysis (FEA). While analytical models are easy-to-use, they may lack the precision needed for accurate lifetime assessments. Conversely, FEA, though more precise, requires expertise, is time-consuming, and may not be cost-efficient. This study aims to present a new analytical model that accounts for the shape of solder joints, with a special emphasis on the determination of the mechanical properties of the Printed Circuit Boards (PCBs) and components. A simplified elastic-plastic constitutive relationship coupled with a viscoplastic model is used to describe the behavior of SAC305 solder joints under temperature cycling. The reliability model presented in this study is calibrated and validated using over 100 durability data points from various leadless packages, PCB stack-ups, and thermal cycling conditions. It represents an efficient and easy-to-use tool for electronic designers to quickly and accurately evaluate the thermomechanical reliability of their electronic assemblies.
The Challenge of Lower Temperature Soldering for Large Ball-Grid Array (BGA) Board-Level Assembly – Phase 1. Processing
Low temperature soldering (reflow peak temperature at 200oC and below) has been considered as one of the effective ways to reduce the processing defects caused by warpage of large BGA assembly. Most of the large BGAs are still surfaced with SnAgCu (SAC) and/or modified SAC balls, whose melting temperature ranges from 210oC to 220oC. Although BGA warpage can be reduced under low reflow temperature, the limited solder paste volume, because SnAgCu ball will not melt but dissolve during reflow, may still be insufficient to compensate for the mitigated warpage, possibly resulting in forming the defective joints, including non-contact, head-in-pillow and non-wet-open etc. Adding more paste would reduce the possibility of forming afore-mentioned defective joints but bring in the risk of joint bridging. Increasing the reflow peak temperature may enlarge the component warpage but allow more molten solder volume during soldering, which may compensate for the warpage displacement and help the joint formation as well. Hot-tearing from using low temperature solder is another concern related to the overlap of component warpage inversion temperature and solder solidification temperature. Thus, optimization of both paste volume and reflow temperature, as well as selection of the appropriate solder alloy are critical to succeed. The current article has systematically, in the first time, investigated the joint formation through the selection of (1) solder alloys of different melting temperature (138oC for BiSnAg eutectic, 205oC for DFLT-1 and 196oC for DFLT-2), (2) paste to ball volume ratio (PBVR of 0.13, 0.25 and 0.5), and (3) reflow profiles (low temperature reflow of 185 and 200oC peak, mid temperature reflow of 210 and 220oC, and traditional SAC reflow of 240oC peak) with a 40x40mm2 PBGA928 component (max concave warpage of -11mil at 100oC and max convex warpage of 34mil at 250oC with inversion temperature of 140oC). Defective joints are always seen under low temperature soldering for all three pastes regardless of PBVR. Increasing reflow temperature to above 200oC improved the joint shape and greatly reduced the defects. Under P220 and PBVR of 0.13, all three pastes have achieved the optimal joints without “fatal” defects. DOE analysis had confirmed the reflow peak is the most impact factor to form the optimal joint, followed by PBVR and alloy selection. SAC/BiSnAg joints were dominated by hot-tearing under low temperature reflows, whose wide pasty range, overlapped with the component inversion temperature of 140oC, is attributed to the higher occurrence. SAC/DFLT and SAC/DFLT-2 had much narrower pasty range and always solidified above the inversion temperature, showing much less hot tearing. The investigation of the joint reliability performance is still ongoing and will be presented in Phase II.
Lead-free Solder, Low-temperature Soldering, Ball-grid array, Reflow, Warpage, Hot-tearing, Head-in-pillow, Assembly.
Copyright (c) 2026 Hongwen Zhang, Francis Mutuku, Huaguang Wang https://creativecommons.org/licenses/by-nc-nd/4.0
Comparison of Electromigration in Tin-Bismuth Planar and Bottom Terminated Component Solder Joints
Electromigration monitoring of bottom terminated component (BTC) solder joints is limited to electrical resistance measurements of the solder balls. Tracking the microstructural evolution such as bismuth segregation in tin-bismuth solder ball, is typically via metallurgical cross sectioning, a destructive technique. Once cross sectioned, the solder ball is not available for further electromigration current stressing. A novel planar solder geometry has been invented and developed that allows real-time, non-destructive monitoring of solder microstructure, while the progress of electromigration can be concurrently tracked via electrical resistance means. Planar solder joints are easy to fabricate in a typical metallurgical laboratory. If the electromigration behavior of the planar and the BTC solder joints happen to be similar, the planar solder joint approach could greatly aid in the quick development of solder alloys by comparing the rates of electromigration and the metallurgical changes in planar solders of various compositions. In this paper, the electromigration rates and behavior of eutectic Sn-Bi alloy in planar and in BTC solder joints were compared and shown to be similar. This important finding opens the use of planar solder joints for the quick and low-cost development of low-temperature solder alloys.
Copyright (c) 2024 Journal of Surface Mount Technology
Cu Conductive Paste as Via Filling Materials for Various Substrates
In this study, we developed a Cu paste that can be used as a filling material for through silicon via (TSV), through glass via (TGV), and organic substrates. Non-through holes with diameters ranging between 20 and 100 μm and depths ranging between 70 and 100 μm (aspect ratios from 1 to 3.5) formed in a silicon surface layer were filled with Cu paste. TGV substrates with diameters ranging between 30 and 90 µm and thickness of 300 µm were filled with Cu paste without cracking. Multilayer substrates with the diameters of 180 and 260 µm and a thickness of 6.4 mm (aspect ratios: 25, 36) were filled with Cu paste without cracking. The 2.5D chip package was prepared using a TSV filled with Cu paste as a 2.5D interposer. The 2.5D chip package was verified through reliability test [thermal cycle test (TCT), high temperature storage test (HTST), un-bias high accelerated stress test (HAST) and pressure cooker test (PCT)]. After the reliability test, the conductive resistance of the package that adopted the Cu paste was found to be within 10% of the initial value. Moreover, we found that Cu paste can be applied to 2.5D interposer as filling material.
Low-temperature metallization, Cu paste, Via filling, TSV, TGV, Organic substrate
The Cleaning process simulation by Glass Test Boards
This article explains the utilization of Glass Test boards for different tasks for the cleaning process building, optimization, and monitoring. We have 12 years of experience building and using Glass Test Boards as a precise tool for comparing material properties, machine settings, and process optimization. Some years ago, we decided to do a joint project with the company Magnalytix and build another kind of test board capable of being optical inspected and tested on the surface resistance. We want to share our experiences and show the advantages of utilizing such glass models for enhancing the quality of the cleaning process and lowering the cost of building the process.
The Intermediate Barrier Performance of Electroless Co-W-B / Ni-P Stacked Deposits Between Cu and Solder Joint
Nickel (Ni) is one of the most common surface finishing materials for solder joint and wire bonding because it can behave as the diffusion barrier for Copper (Cu) and bring excellent reliability. Electroless Ni plating has many advantages such as high productivity, good thickness uniformity, and the deposition ability for isolated patterns of printed circuit boards without supplying electrolytic power. Electroless Ni plating is widely used as the jointing material for Tin (Sn) or Sn alloy solder in printed circuit boards, lead frames, and so on. The amorphous deposits of electroless Nickel-Phosphorus (Ni-P) generate the intermetallic compounds (IMC) with solder after the reflow and the remaining Ni behaves as the barrier between Cu and solder. In this time, the P amount of Ni-P deposits generally have the impact to the growth of IMC. Electroless Ni-P with high P (high P Ni) such as 10-12 wt% has been selected to achieve both corrosion resistance and solder joint reliability. Because the growth of Sn-Ni IMC between high P Ni is faster than deposits with lower P, the target thickness of high P Ni has been set to approximately 10 µm to sustain the Ni-P layer as the barrier layer between Cu and solder during reflow. However, if the Ni-Sn IMC is repeatedly formed and dissolved by the diffusion after solder jointing, the Ni-P layer reduces and finally disappears. As a result, an additional barrier layer is desirable for higher reliability. In this study, we investigated adding electroless Cobalt-Tungsten-Boron (Co-W-B) as a new intermediate barrier between Cu and solder jointing. We evaluated the bonding strength and IMC analysis after mounting Sn-Cu-Ni-P type solder on Cu/Co-W-B/Ni-P by using different reflow profiles. Results showed that Co-W-B 0.1-0.2 µm/Ni-P 1-2 µm stacked deposits had excellent bonding strength even though the Ni-P thickness is thinner such as 1 µm. After mounting solder, a P-rich layer was generated on the Co-W-B layer in cross-sectional Transmission Electron Microscope (TEM) observation. Scanning Transmission Electron Microscope (STEM) –Energy Dispersive X-ray Spectroscopy (EDS, STEMEDS) analysis showed the P-rich layer and Co-W-B layer prevented diffusion between solder and Cu. Furthermore, even if after the thermal loading of high temperature, the bonding strength was excellent. Additionally, the cross-section analysis of STEM-EDS revealed that a thin layer composed of Ni, Co and P was formed between Co-W-B and the P-rich layer. This thin layer also might behave as the barrier for solder. In conclusion, Co-W-B / Ni-P stacked deposits exhibited excellent reliability as the additional intermediate barrier layer between Cu and solder.
Condition Monitoring System: A Flexible Hybrid Electronics Approach for Sealed Container Applications
A comparative study is presented between two advanced flexible hybrid electronics (FHE) systems designed for monitoring temperature within storage containers across various industries, including food, pharmaceuticals, agriculture, automotive, and defense. The first system, a copper-flex system (CFS), employs an 88.9 µm polyimide substrate with 35 µm thick copper traces, coated with a 12.5 µm polyimide solder mask. The second system, a printed-flex system (PFS), utilizes a 127 µm polyimide substrate with high-temperature resistance and tensile strength. Conductive silver ink was screen-printed on the PFS substrate, and electronic components including a temperature sensor were attached. Functional and reliability tests were performed to check the accuracy and durability of the temperature sensor. Further, environmental and mechanical characterizations including moisture and insulation resistance, corrosion, elongation, bending, and terminal bond strength tests were performed based on ASTM and IPC-TM650 standards. Moisture and insulation resistance test on the PFS test coupons without a coating layer indicated stable resistance of approximately 18 MΩ, while permanent color change indicated oxidation of copper on uncoated CFS test coupons. After 72 hours of corrosion test, both the CFS and PFS “meander line” test coupons covered with polyimide showed negligible change in weight and resistance, approximately 0.35%. A Young’s modulus of 7.17 GPa and 2.6 GPa was calculated from the elongation test for the CFS and PFS, respectively. Bending tests on PFS revealed negligible average resistance change (0.1%) during 180° bending cycles, while no impact was recorded on the CFS. During the terminal bond strength test, soldered wires detached from the CFS test coupons at an average force of 43 N, while it was 3.8 N on the PFS test coupons. Both systems with polyimide coating layer demonstrate robustness and reliability for diverse applications in various industries.
Intermetallic Compounds in Solder Alloys: Common Misconceptions
Intermetallic compounds (IMC) or intermediate phases are formed between two or more metallic elements in many metal alloy systems. During soldering, an IMC is formed at the soldered interface as the molten solder reacts with an element in the substrate. IMCs also can form within the bulk solder as the joint solidifies. IMCs have critical roles in the solder joint quality and reliability. Unlike most metal alloys, an intermetallic compound typically has a fixed stoichiometry and is in variance with the conventional phases or constituents in the metal system (e.g., alpha and beta). IMCs have a different crystal structure than any of its constituents and some but never all the characteristics and properties of its constituents. Ductility is an important solder joint property, and the low intrinsic ductility of IMCs is associated with brittle behavior and reliability risk in service. However, a review of published solder field failures shows little evidence that IMC properties or IMC evolution under service conditions reduce solder joint reliability. Most IMC-induced solder joint failures are found to result from incorrect material specification or uncontrolled soldering processes. This paper describes the IMCs that occur typically in eutectic, Sn63Pb37 solder and near-eutectic SAC305 or other tin-based Pb-free solder alloys, including how they impact solder joint reliability. The paper also describes the potential impact of IMCs on the solder joint reliability for the newest generation of Pb-free high-performance solder alloys.
Solder is a critical component in modern electronic systems – past, present, and future. While solder is used within packaged electrical devices, the highest volume of solder is used for fabrication of printed circuit board assemblies. Historically, tin-lead solder was the dominant solder used in printed circuit board assemblies. However, tin-silver-copper solder replaced tin-lead solder starting in 2006 after European Union regulations banned the use of lead for a wide range of electronic products. Despite the successful transition to tin-silver-copper lead-free solder and over fifteen years of high volume lead-free electronic production, a number of aerospace and defense products have not converted to tin-silver-copper or other lead-free solders over reliability concerns. Reliability should be a concern for all product manufacturers and end-users. This begs the question, what has convinced industries that are currently producing lead-free products that the reliability was sufficient and what is keeping defense and aerospace electronic equipment manufacturers from adopting lead-free solder. This paper reviews decision processes for adopting solder for printed circuit board assembly.
Conformal Coating Testing in Various Test Environments
Conformal coatings have traditionally been tested by determining the mean time to failure of conformally coated hardware exposed to corrosive test environments. This test approach has serious shortcomings: The test temperatures are most often too high. At these high temperatures, the conformal coating properties may be quite different from those at the application temperatures. In addition, the times to failure are unacceptably long extending into many months. Overcoming these shortcomings is an iNEMI championed test that involves exposing conformally coated thin films of copper and silver to sulfur vapors at 40-50 oC in flowers of sulfur (FoS) chamber and using the corrosion rates of the coated metal thin films as a measure of the corrosion protection capabilities of the conformal coatings. The test temperatures are similar to the application temperatures, the test durations are no more than a week and can be conducted under various temperature and humidity conditions. The purpose of this paper was to determine if testing in the industry-standard mixed-flowing gas corrosion chamber would give similar results as those using the FoS chamber. Acrylic, fluorinated acrylate, and atomic layer deposition conformal coatings were tested in three environments: (a) flowers of sulfur (FoS), (b) mixed-flowing gas (MFG), and (c) iodine vapor. The performance of the coatings tested in the FoS and the MFG corrosion chambers were quantitatively similar. The iodine vapor test results were in qualitative agreement with the FoS and MFG test results. In addition, we present early results pointing to the utility of terahertz-frequency imaging as a technique for measuring conformal-coating thickness nondestructively.
Effect of Matte-Sn Electroplating Parameters on the Thermo-mechanical Reliability of Lead-free Solder Joints
Most of the Cu/Cu alloy lead-frames of electronic components used for automotive applications contain electroplated matte-Sn terminal finish to improve the wettability of Sn-based Pb-free solders during reflow soldering process. When the solder joints are subjected to combined thermal and mechanical cyclic loading, the influence of matte-Sn electroplating parameters can lead to early and brittle failure of the solder joint. To test this hypothesis, a factorial design of experiments (DOE) has been conducted with LFPAK-MOSFET (hereafter referred to as LFPAK) components plated with different matte-Sn electroplating parameters and reflow soldered with two solder alloys (SAC 305 and Innolot). The LFPAK solder joints were then subjected to thermo-mechanical in-phase cyclic loading under different strain amplitudes. No electrical measurement is done to eradicate the effect of electrical current on the solder joint. The response to the DOE is the crack percentage obtained in the LFPAK solder joints after 1000 and 2000 cycles. The Innolot solder joints exhibited lower crack percentages than the SAC 305. The level of organic additives in the electroplating process of matte-Sn influences the failure mode of the solder joint. Microstructural investigation attributes the nature of failure to the morphology of the (Cu,Ni)6Sn5 IMC phase that forms on the component side of the solder joint.
Freeze Frame Reflow to Enhance Yields for Advanced Low-Profile Bottom Terminated Packages
Today, designers are demanding an overall form-factor reduction to save board space, increase functionality, and allocate more circuit board real estate toward end-user applications – all with less space allocated to power management where not just the X-Y shrink but the 3D volumetric shrink is required. Unlike most gull wing style leaded packages, QFNs (Quad Flat Pack No lead packages) also known as BTCs (Bottom Terminated Components) have coplanar terminals below the package body to answer this ever-decreasing form-factor requirement. The final standoff in these QFN style packages are dictated by the solder joint geometry formed. Within this advanced package family also finding a similar trend are power WCSPs (Wafer Chip Scale Packages) where traditional solder spheres are being replaced with low profile interconnects in expanded and asymmetrical geometries. This paper presents factors that influence advanced low standoff package solderability performance with the use of video microscopy and live in situ X-ray reflow. To reflect the QFN board assemblies that are typically designed a series of layouts were implemented across different coupon test boards. Assembled coupon test board were designed by varying 1) through hole via design, 2) solder mask tenting techniques, 3) periphery and center thermal pad printed solder joint volumes, 4) no-clean and water-soluble solder paste flux chemistry all using SAC 305 alloy and type 4.5 powder size. One case study using live in-situ X-ray system will explain the effects of a QFN land pattern layout incorporating vias in the center thermal pad with solder mask tenting over the via openings located on the back of the PCB. In another configuration vias were removed from the center thermal pad and vacuum reflow performed during the liquidus phase of the solder with an explanation of why some of the voids remained. The first and second order results presented within this paper have practical implications and from their observations a novel process evaluation technique coined as Freeze Frame Reflow (FFR) was developed. In the last case study presented, an advanced mrQFN (multi-row QFN) package is investigated for factors affecting yields. FFR is then implemented resulting in an increase in yield further demonstrating the benefits this new & novel technique can offer.
Copyright (c) 2023 Journal of Surface Mount Technology
Pb-Free Solders and Aerospace/Defense (A&D) High Performance Considerations
The Aerospace & Defense (A & D) industries maintain a high level of interest in the expansive amount of work performed in developing and qualifying Pb-free solder alloys. The three main areas of interest continue to be thermal cycle, mechanical shock, and vibration. The past twenty years have seen an unprecedented increase in alloy development such that the concepts of “generations of solders and “families of solders” have been coined to help manage the numerous individual alloys on the market today. This paper will discuss work done with Pb-free solder alloys, many with the addition of constituents focusing on varying property enhancements. The purpose is to provide a “snap shot” summary of progress to date and relate perspectives both as advantages and concerns solely in a constructive manner to aid researchers in planning their next steps in development and qualification of these alloys.
Solderability of Additively Manufactured Copper Surfaces
As additive manufacturing technology for copper rapidly evolves, the likelihood for downstream joining like soldering and brazing exists. A solderability study was performed to assess process fundamentals over a variety of AM approaches. The solderability of 7 different copper (Cu) surface types were evaluated using the wetting balance technique: 4 Cu coatings (CP-007 and CP-008 conductive copper pastes, IMC-4118 conductive laser sinter paste, IMC-2501 copper ink), 2 laser processed Cu surfaces, and 1 bulk additively manufactured (AM) Cu coupon type. Laser processed surfaces were subjected to either circular or linear laser raster patterns. AM coupons were fabricated via a powder-bed laser process. In-situ force measurements were recorded while coupons were dipped into and removed from a 63Sn-37Pb (SnPb) or 96.4Sn-3.0Ag-0.6Cu (SAC305) solder bath, allowing contact angles and surface energies to be calculated. Meniscus height values were also measured. Surfaces were characterized before and after dipping via optical and electron microscopy. Results conclusively indicated that although all samples were intended to represent pure Cu, wettability was found to be strongly dependent on surface type with several samples exhibiting no wetting. Although the CP-007 paste performed the best of any non-traditional surface, all nontraditional surfaces saw signifi cant wettability improvements with aggressive cleaning via HCl etching.
Mechanical Characterization of SAC305 and SnPb36Ag2 BGA Assemblies Under Static Flexural Loading
Static bending-induced solder joints damage is a main reliability concern for aerospace and military industries whose Printed Circuit Board Assemblies (PCBAs) are required to remain functional under flexural loading. In order to dissipate heat in an equipment, it is common to install thermal gap pads on electronic packages. When compressing thermal gap pads during the fixture process, the PCBA can bend and solder joints can therefore crack if the deflection is too important. This paper reports the durability of 96.5Sn-3.0Ag-0.5Cu (SAC305) and 62Sn-36Pb-2Ag (SnPb36Ag2) Ball Grid Array (BGA) assemblies under static flexural loading at -55°C, 20°C and 125°C. As electronic equipment can be stored at high temperature for prolonged durations, some SAC305 test vehicles were also aged at 125°C for 192 hours. For each test configuration, the bending tests were conducted at a ramp-rate of 2 mm/min and the central displacement-to-failure was measured. Finite Element Modeling (FEM) analysis was conducted considering a global-local approach and the transfer function between the central displacement-to-failure and the local PCB strain near the critical solder joints was determined for each test configuration. The results give the necessary data for designers to assess whether a specific PCBA design subjected to static bending is at risk or not.
A Novel Method of Incorporating CNT into Additive Manufacturing Electronics Dielectric Material
Flexible Hybrid Electronics (FHE) Parts that are additively manufactured give engineers and designers greater flexibility in geometry, complexity, and variety or customizability. In this work, UV curable dielectric materials for additive electronics and incorporated Carbon Nano Tubes (CNTs) within a formulated UV/LED curable matrix was used. It will be shown that inkjet printing CNT mixture in specific manner with a commercial UV curable dielectric improves mechanical and thermal properties of the final dielectric compared to the dielectric without the CNT mixture, including a significant decrease in the coefficient of thermal expansion, while keeping excellent electrical properties.
Aerosol Jet Printed Interconnects for Millimeter-Wave Components
As millimeter wave RF device applications expand above traditional microwave frequency bands in the global communications, automotive and Mil-Aero markets, the need to limit interconnect signal losses related to parasitic elements has never been more important. As the frequency increases, device designers are facing numerous challenges, complications, and costs when fabricating interconnects with techniques such as copper pillar bumps, wire, ribbon or wedge bonding in 3DIC packaging. Printing conformal interconnects with Aerosol Jet® direct-write technology can offer package designers and RF engineers a new approach for optimizing interconnect transitions to active die, tailoring the loss characteristics to specific application requirements and eliminating the need to compensate for high signal transmission losses. Printed interconnects can be digitally designed into the package with a variety of metallic and dielectric materials. As these interconnects are conformally printed on the 3D surface of the package, the trace length can be minimized with zero loop height, reducing parasitic inductance to active die circuitry specifically for die on board, die in trench, or die on die with pads-up packaging configurations. In this work, Aerosol Jet® printed interconnects with silver nanoparticle inks are compared with the gold microstrip transmission lines as well as traditional gold bond wires, for performance up to 110 GHz. We will share examples showcasing that the printed interconnects can have similar RF transmission performance to microstrip, with significantly lower loss than bondwires especially at high frequencies. We will also discuss design effects for Aerosol Jet® printed RF interconnects up to 110 GHz based on a set of results for different line heights with a given line width printed with a silver ink.
Conformal interconnects, millimeter-wave component, Aerosol Jet® printing, direct-write technology
Modeling the Effects of Thermal Pad Voiding on Quad Flatpack No-lead (QFN) Components
Finite element modeling was used to evaluate the effects of thermal pad solder voiding on the thermal resistance of Quad Flatpack No Lead components. This included two different approaches for modeling solder voids: many small, distributed voids, the effects of which were averaged across the entire solder contact area or a single discrete void. Two approaches were used for defining the thermal path established in the solder. The effects of other design parameters - thermal boundary conditions, the presence of thermal vias under the package, and the size of the die power dissipation area – were also addressed. Modeling showed that thermal vias and external boundary conditions had the most significant impact on the package thermal resistance. Solder pad voids and concentrated die-level heat dissipation, for the range used in this study, had noticeable but less significant impacts on thermal resistance. The study also compared different approaches for simulating solder voiding and identified ranges in which modeling simulations are most appropriate.
Lower Temperature Soldering Using Supercooled Liquid Metal
Lead-free solder metal alloys can be formed into supercooled liquid metal microcapsules and used to create solid full metal interconnects at dramatically lower processing temperatures. These alloys can be made with or without bismuth. The technology encapsulates known and established RoHS compliant solder alloys inside a thin oxide/organic shell nanofilm that keeps the metal in a metastable supercooled liquid state at ambient temperatures. The thin oxide/organic shell can be mechanically broken or chemically dissolved to release the liquid metal that then rapidly solidifies all without requiring heat. The novel solder interconnect technology avoids thermal damage to components and materials, or quality issues caused by coefficient of thermal expansion mismatch.
An Investigation on the Influence of Nickel Contamination of Plated Through Hole (PTH) Solder Joint Integrity
An investigation was conducted to examine the validity of current industry maximum nickel contamination limits, which are established to ensure plated through hole solder joint integrity, for SnPb and SAC305 solder baths. Test vehicles were processed using three levels of nickel contamination for each solder: 0.01 wt.%, 0.02 wt.%, 0.05 wt.% for SnPb solder and 0.05 wt.%, 0.07 wt. %, 0.10 wt.% for SAC305 solder. The test vehicles were subjected to thermal cycle testing in accordance with the IPC-9701 specification. Based on this testing, the authors recommend that the allowable nickel contamination levels listed in the IPC-J-STD-001 specification (Table 3-1, Maximum Limits of Solder Bath Contaminant) be 0.05 wt.% for SnPb Assembly, 0.05 wt.% for SnPb Preconditioning, and 0.10 wt.% for SAC305 Pb-free Assembly.
Copyright (c) 2022 Journal of Surface Mount Technology
The Influence of Element Lead (Pb) Content in Tin Plating on Tin Whisker Initiation/Growth
The implementation of the Restriction of Hazardous Substances (RoHS) European Union (EU) Directive in 2005 resulted in the introduction of pure tin as an acceptable surface finish for printed circuit boards and component terminations. A drawback of pure tin surface finishes is the potential to form tin whiskers. Tin whiskers are a metallurgical phenomenon that is associated with tin rich/pure tin materials and has been a topic of intense industry interest. The acceptance and usage of pure tin by the electronics industry component fabricators is understandable as the pure tin surface finishes are inexpensive, are simple plating systems to operate and have reasonable solderability characteristics. However, high performance/harsh environment electronics typically have product life cycles that are measured in decades and therefore are much more susceptible to the potential long term threat of tin whiskers. The GEIA-STD-0005-2 “Standard for Mitigating the Effects of Tin Whiskers in Aerospace and High Performance Electronic Systems” established the definition of the term “Pb-free tin” as : “Pb-free Tin is defined to be pure tin or any tin alloy with <3% lead (Pb) content by weight. A functional definition of “pure tin” was necessary so that the electronics industry could establish tin whisker risk protocols against a known acceptable target value in terms of soldering materials and processes. An investigation was conducted to determine the influence of 1% - 5% elemental lead (Pb) content in tin plating on tin whisker initiation and growth. The investigation results were used in the revision of the GEIA-STD-0005-2 “Standard for Mitigating the Effects of Tin Whiskers in Aerospace and High Performance Electronic Systems” specification technical discussions.
The Dissimilar Self-Alignment Characteristics of Smaller Passive Components in the Length and Width Directions
Motivation: As passive components’ size gets smaller, quality rejects due to overhang and misalignment after the reflow appear more frequently. This situation is partly because the pass-fail criterion is set based on the offset concerning the component dimensions. Therefore, understanding the self-alignment characteristics of electronic components becomes very critical for surface-mount assembly yield. This research investigates the dissimilarity of self-alignment in the length and width directions. Approach: To avoid the argument of sample to sample variations, data are collected from 81 printed circuit boards (PCB) and 182,250 assembled components. Within a PCB, 25 different solder paste printing offset locations and 81 component placement offset settings are implemented. Component-placement positions before and after the reflow are monitored. The results are compared to identify different component sizes’ self-alignment characteristics in the length and width directions. Key findings: The misalignment of smaller passive components, e.g., R0402M(0.40 mm × 0.20 mm), is worse than the larger component under the identical solder paste printing and component placement conditions. Furthermore, the self-alignment characteristic in the length direction of these passive components, e.g., R0402M, to R1005M (1.00 mm × 0.50 mm) is superior to that of width direction. The observations are not consistent with the results found in earlier research that reported on larger components, e.g., C0402M(0.40 mm × 0.20 mm), to C3216M(3.20 mm × 1.50 mm).
SMT assembly, smaller passive components, self-alignment in length, self-alignment in width
Copyright (c) 2021 Journal of Surface Mount Technology
Miniaturized Stacked Die QFN for Tire Pressure Monitoring System Applications
Tire Pressure Monitoring Systems (TPMS) are electronic wireless systems that monitor and report air pressure inside pneumatic tires in real time. An example of a TPMS module integrated with the valve stem and showing the typical tire mounting location is shown in Figure 1. For their safety and fuel economy benefits, starting with the mid-2000's, active TPMS were mandated on many vehicles worldwide. The NHTS estimates that there are approximately 23,000 accidents and 535 fatalities annually involving tire underinflation and blowouts [1]. The use of TPMS has been shown to result in improved fuel economy and therefore reduced carbon emissions [2]. TPMS in passenger vehicles was mandated in the US as of Sept. 1, 2007 under the TREAD Act, in the European Union as of Nov. 1, 2012 and in South Korea as of Jan.1, 2013. Countries like Russia, Indonesia, the Philippines, Israel, Malaysia, Turkey and many others soon followed [3]. The first TPMS systems were large and bulky with a significant electronics content [4]. Since that time TPMS electronics have gotten more energy efficient and form factors have come down dramatically. This paper will outline an effort to miniaturize an existing 1.0 mm pitch, 7x7x2.2 mm body size 24 lead QFN (Quad Flat No Leads) TPMS down to a 4x4x1.98 mm body size QFN with 0.5 mm pitch that would still meet automotive AEC Grade 1 reliability requirements. The original 7x7 mm three die QFN package consisted of an ASIC, a pressure sensor and an accelerometer. This miniaturization led to many technical challenges at both the package and board level. This paper will primarily address the board level reliability (BLR) challenges encountered due to the large silicon to package ratio along with the 50% reduction in pitch. Through a series of test vehicles with variables such as QFN leadframe surface finish, lead shape and size, wettable flank (WF) technology and anchors pads, the BLR was successfully improved to the point where it met application requirements.
QFN, Board Level Reliability, BLR, Tire Pressure Monitoring System, TPMS, NiPdAu, pre-plated leadframe, PPF, intermetallic, IMC, step-cut, dimple.
High Density RDL Technologies for Panel Level Packaging of Embedded Dies
The ongoing miniaturization and functional heterogeneity in electronics packaging are pushing the demand for advanced substrate technologies. Highly integrated, advanced multi-chip packaging solutions combine application, logic and computing dies with memory or components for power management in a single package. A solution to achieve low fabrication costs is the close embedding of thin dies in IC Substrates based on large formats (600 x 600 mm²), known from PCB fabrication. In a consortium of partners from industry and research advanced technologies for Panel Level Packaging (PLP) are developed. This paper will show the development of 5µm L/S RDL routing density and chips with 50µm bump pitch. Here, the 6x6 mm² dies are symmetrically embedded into an organic laminate matrix. A PCB core (100µm thickness) with very low coefficient of thermal expansion (CTE) containing laser cut cavities is used, acting as a frame layer. Besides mechanical and handling stability, the usage of such a frame offers the advantage of pre-integrating additional features like local fiducials, through vias or power lines by conventional PCB processes. Within that frame, the dies are embedded by lamination of an organic build-up film with 25µm thickness equal to bump height. The chip contacts are then opened without the need of any micro via formation. Here a strong focus is set on RIE etching of the polymer material. Highly accurate measurement of the real die position is essential for the following processing. The formation of the redistribution layer (RDL) is done in a semi-additive process (SAP) utilizing sputtering technique and direct imaging (LDI). To achieve the fine pitch demands, an adaptive imaging process is applied. Therefore, a newly developed LDI machine is used to write structures in a 7µm photoresist. This exposure also combines the measurement data of the real die position and the adaption of the exposure artwork, in order to achieve highest registration quality.
A Gauge Study of an Intercomparison Evaluation to Implement the use of Fine-Pitch Test Patterns for Surface Insulation Resistance (SIR) Testing of Solder Fluxes
SIR is a recognised tool for establishing electrochemical reliability of electronic assemblies. Currently the test patterns in the standards reflect coarse pitch components. An intercomparison has been completed with the aim of establishing the introduction of a fine pitch SIR pattern with a 200µm gap. This exercise included the contribution from seven international participants. This new pattern moves the test method forward into the realm of current technologies where components of this pitch are common place. The study reported here validates the basis for the introduction of the new pattern, and confirms acceptable Gauge R&R for the SIR technique. The analysis also highlights the challenges in controlling humidity to achieve comparable results between different users. The results also point to the challenges in achieving acceptable Gauge R&R when measuring resistances >1011Ω.
SIR testing, Gauge R&R, Humidity sensitivity, Update to standards, Fine pitch, Electrochemical reliability
Board Level Reliability of Automotive Grade WLCSP for Radar Applications
Wafer-Level Chip Scale Packages (WLCSPs) are becoming commonplace in the industry due to their small form factor. Applications include industrial and automotive which demand high reliability performance. Additionally, WLCSPs may be superior in some implementations to other package options for RF performance in the mmWave spectrum, which is desired for automotive radar application. But board level reliability can be a challenge for some WLCSP package due to CTE mismatch between Si and PCB. Variety of factors including PCB materials, sphere alloys, and board level underfills can influence the board level reliability of WLCSP packages. In this study the industry’s first auto grade 1 capable large WLCSP package. (~ 72 mm2 body size, 18x15 BGA array, 0.5 mm pitch) is presented. Board level underfill application was utilized to achieve automotive grade board level reliability. Underfills are typically selected based on thermomechanical properties of unaged materials. An understanding of the evolution of underfill material properties under thermal aging is important for selecting a stable material capable of meeting the reliability requirements. This study evaluates board level underfills and edge bond materials in the form of stand-alone samples and applied to a large daisy-chain WLCSP. The underfilled daisy-chain WLCSPs and the stand-alone samples are placed in a ‑40/125C air cycling chamber (1 cycle/hour). Glass transition temperature (Tg), elastic modulus (E), and coefficient of thermal expansion (CTE) are measured using Dynamic Mechanical Analysis (DMA) and Thermomechanical Analysis (TMA) on the stand-alone samples at various intervals to monitor the evolution of material properties. Simultaneously, the underfilled daisy chain WLCSPs are monitored electrically using an event detector. The combination of material property measurements and cycles to electrical failure can be used to correlate underfill material properties and WLCSP board-level reliability. The results of this study can provide material property guidance for underfill selection.
Tin Whisker Formation on Small Outline Transistors Assembled Using Bismuth-Containing Lead-Free Solder Alloys After Long-Term Ambient Temperature, High Humidity Storage Part 3: In-Depth Characterization and Mechanisms
With the introduction of environmental legislation such as the Restriction of Hazardous Substances (RoHS), lead (Pb)-free materials have made their way into the electronics manufacturing industry. One issue that has emerged is that Pb-free solder alloys can initiate and grow tin whiskers under specific conditions. These whiskers are thin, highly conductive filaments which have the potential to grow and can cause field failures in many applications. Most concerning with respect to tin whiskering are high reliability applications such as aerospace, automotive, and medical. Bismuth (Bi) is being considered for inclusion in solder alloys to replace the current industry standard (SAC 305) and provide improved thermomechanical and vibration reliability. In this paper, we discuss whisker formation of several Bi-bearing alloys after long-term (12,000 hours), ambient high humidity (25°C/85% RH) storage. Three alloys containing Bi, in addition to SAC 305 (Sn-3.0Ag-0.5Cu), were considered. These alloys were Violet (Sn-2.25Ag-0.5Cu-6.0Bi), Sunflower (Sn-0.7Cu-7.0Bi), and Senju (Sn-2.0Ag-0.7Cu-3.0Bi). The boards were fabricated with electroless nickel immersion gold (ENIG) and immersion tin (ImmSn) finishes and populated with parts having Cu and Fe42Ni alloy leads and chip parts, with half of assemblies cleaned and half cleaned and contaminated with low levels of NaCl. This paper is the third in a series of three in which we share more in-depth characterization of features of interest from the small outline transistor (SOT) inspection. Discussion regarding the role of Bi in the overall stress state of the joint will also be provided.